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MITSUBISHI (Dig./Ana. INTERFACE)
M62376GP
8-BIT 12CH D-A CONVERTER IC BUILT-IN 12-BIT I/O EXPANDER
DESCRIPTION
The M62376GP is a semiconductor IC that adopts a CMOS structure having 12-channel of 8-bit D-A converter and 12-bit I/O expander. The IC has achieved a wide operation range of 2.7V to 5.5V in power voltage. Data is easily available via 3-wire combination system serial input of SI, CLK and EN. The IC also provides an SO pin enabling cascade connection. It provides 8 pins that share D-A converter and I/O ports that can be arbitrarily switched with serial input data.
PIN CONFIGURATION (TOP VIEW)
A1 1 A2 2 A3 3 A4 4 D11/A5 5 D10/A6 6 D9/A7 D8/A8 7 8 9 24 GND 23 REST 22 EN 21 SO 20 SI 19 CLK 18 D0 17 D1 16 D2 15 D3 14 VCC 13 VDD
FEATURES
Supply voltage 2.7 to 5.5V Adopts 4 special ports for each of DAC and I/O and 8 ports that share DAC output and I/O. Each port can be set by serial data for input/output status. Built-in power-on reset where D-A output is set to "L" in the initial status and I/O goes to Hi-impedance when power is turned on. Small package of 0.65mm pitch and 24 pin.
D7/A9
D6/A10 10 D5/A11 11 D4/A12 12
Outline 24P2E-A
APPLICATION
Adjustment/control of industrial or home-use electronic equipment, such as VCR camera, VCR set, TV, and CRT display.
BLOCK DIAGRAM
RESET 23 SI EN CLK 20 22 19
CLOCK CONTROL CIRCUIT
VDD 13
VCC 14
GND 24 SHIFT REGISTER
21 SO S5 S4 S3 S2 S1 S0
S15 S14 S13 S12 S11 S10 S9
S8
S7
S6
DECODER
8-BIT LATCH
8-BIT D-A CONVERTER
***
8-BIT LATCH
8-BIT D-A CONVERTER
8-BIT LATCH
8-BIT D-A CONVERTER
******
8-BIT LATCH
8-BIT D-A CONVERTER
Amp. Hi-Z 8-BIT LATCH I/O SELECT 12-BIT LATCH
***
******
(12)
*** A1 A4 A5
****** A12
****** ****** OUTPUT DATA 8-BIT LATCH
OUTPUT DATA 4-BIT LATCH
1 A1 ***
4 A4
5 D11/A5 ******
12 D4/A12
15 D3 ******
18 D0
MITSUBISHI (Dig./Ana. INTERFACE)
M62376GP
8-BIT 12CH D-A CONVERTER IC BUILT-IN 12-BIT I/O EXPANDER
EXPLANATION OF TERMINALS
Pin No.
20 21
Symbol SI SO CLK EN A1 A2 A3 A4 D11/A5 D10/A6 D9/A7 D8/A8 D7/A9 D6/A10 D5/A11 D4/A12 D0 D1 D2 D3 VCC GND VDD RESET
Function Serial data input pin. Enters serial data of 16-bit in length. Outputs data from 16-bit shift register that reads serial data or parallel data. Shift clock input pin. At the rise of shift clock, input signal from the SI pin is entered into the 16-bit shift register. Entry of low level into the EN pin starts to read data. Putting 16-bit data at high level after input loads the input data to a specified register.
19
22 1 2 3 4 5 6 7 8 9 10 11 12 18 17 16 15 14 24 13 23
Special output pin for 8-bit D-A converter (DAC)
Pin that shares I/O and DAC output. Settings can be selected with serial data. D4 to D11 are connected to the VDD power supply.
Digital input output pin.
Digital block power supply pin. GND pin Power supply pin in analog block and reference voltage input pin on the upper side of D-A converter RESET pin
MITSUBISHI (Dig./Ana. INTERFACE)
M62376GP
8-BIT 12CH D-A CONVERTER IC BUILT-IN 12-BIT I/O EXPANDER
EXPLANATION OF TERMINALS BLOCK DIAGRAM
VDD 13 EN 22
CLOCK CONTROL
VCC 14
GND 24 [1110]
CLK 19 SI 20
POWER ON RESET
Di11 Di10 Di9 Di8 Di7 Di6 Di5 Di4 Di3 Di2 Di1 Di0 EN SHIFT REGISTER CLK S15 S14 S13 S12 S11 S10 S9 S8 S7 S6 S5 S4
21 SO S3 S2 S1 S0
RESET 23
LEVEL SHIFT LEVEL SHIFT EN
DECODER (12) DECODER (4)
EN
***** [0000]
8-BIT LATCH
8-BIT D-A CONVERTER
***
8-BIT LATCH
8-BIT D-A CONVERTER
8-BIT LATCH
8-BIT D-A CONVERTER
******
8-BIT LATCH
8-BIT D-A CONVERTER
8-BIT LATCH
[11010000] (A5 to A12 Hi-Z)
[1111]
***
******
(8) *** A1 A4 A5 ****** A12
LEVEL SHIFT
LEVEL SHIFT (8)
12-BIT LATCH
(12)
[1101]
LATCH (8) 1 A1 *** 4 A4 5 D11/A5 ****** 12 D4/A12 15 D3
LATCH 16 D2 17 D1 18 D0
(4)
MITSUBISHI (Dig./Ana. INTERFACE)
M62376GP
8-BIT 12CH D-A CONVERTER IC BUILT-IN 12-BIT I/O EXPANDER
DATA STRUCTURE
Serial data MSB S15 S14 S13 S12 S11 S10 S9 S8 S7 S6 S5 S4 S3 S2 S1 LSB S0
Data for DAC and I/O expander
Address data
Address data S3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 S2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 S1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 S0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Setup (a) A1 selection A2 selection A3 selection A4 selection A5 selection A6 selection A7 selection A8 selection A9 selection A10 selection A11 selection A12 selection I/O expander (serial parallel conversion) I/O expander (parallel serial conversion) I/O expander status setup
* I/O expander (serial
parallel conversion)
Outputs data on S4 to S15 to pins D0 to D11. S3 1 S2 1 S1 0 S0 1
* I/O expander (parallel
serial conversion)
Writes data on D0 to D11 pins into S4 to S15. When next data communication is provided, outputs data sequentially from SO pin at the rise of the shift clock (CLK). S3 1 S2 1 S1 1 S0 0
* I/O expander status setup register Sets input/output pin of I/O expanders. Data "0": Input mode (Hi-Z status) "1": Output mode S3 1 S2 1 S1 1 S0 1
Data
S15 S14 S13 S12 S11 S10 S9 S8 S7 S6 S5 S4
Pin DAC data S15 0 0 0 1 1 X
X :Don't care
D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
S14 0 0 0 1 1 X
S13 0 0 0 1 1 X
S12 0 0 0 1 1 X
S11 0 0 0 1 1 X
S10 0 0 0 1 1 X
S9 0 0 1 1 1 X
S8 0 1 0 0 1 X
S7 X X X X X X
S6 X X X X X X
S5 X X X X X X
S4 0 0 0 0 0 1
(*)
Analog output voltage (Reference voltage on the lower side=0.0V fixed)
(VDD/256)X1 [V] (1LSB) (VDD/256)X2 [V] (2LSB) (VDD/256)X3 [V] (3LSB) (VDD/256)X255 [V] (255LSB) VDD [V] (256LSB)
High-impedance (I/O expander selected)
(*): Only A5 to A12 outputs are available for DAC output by S4 and Hi-Z conversion.
(a) Command to set DAC output to High-impedance (DACHiZ command) S15 X S14 X S13 X S12 X S11 X S10 X S9 X S8 X S7 1 S6 1 S5 0 S4 1 S3 0 S2 0 S1 0 S0 0 Analog output voltage Sets D-A output of A5 to A12 to High-impedance.
MITSUBISHI (Dig./Ana. INTERFACE)
M62376GP
8-BIT 12CH D-A CONVERTER IC BUILT-IN 12-BIT I/O EXPANDER
(b) Initial status just after power is turned on: Low level output from A1 to A4 (set to [00]h) D4/A12 to D11/A5: DAC output of High-impedance (Hi-Z), I/O of input mode (Hi-Z) D0 to D3 :input mode (Hi-Z)
Note: To change the status of pins D4/A12 to D11/A5, switch both analog and digital after setup of High-impedance.
(c) The DACHiZ command is effective only for DAC settings (A5 to A12), but not for the I/O ports (D0 to D11)
TIMING CHART (MODEL)
EN
***
CLK
***
***
SI PARALLEL INPUT D0 to ( SERIAL OUTPUT) D11 (SERIAL INPUT ) D0 to PARALLEL OUTPUT D11 H-Z
S0
n-1
***
S15
n-1
S0
n
S1
n
S2
n
S3 ***
S12 S13 S14 S15
n n n n
***
***
SO
S15 S0 *** n-3 n-2
S15 n-2
H-Z
S15 S0 S1 S2 S3 *** n-2 n-1 n-1 n-1 n-1
S12 S13 S14 S15 n-1 n-1 n-1
H-Z
A1 to A12
***
***
ABSOLUTE MAXIMUM RATINGS
Symbol VCC VDD VIN Vout VIN Vout Pd Topr Tstg Parameter Digital supply voltage Analog supply (D-A converter upper reference voltage) Input voltage Output voltage Input voltage Output voltage Power dissipation Operating temperature Storage temperature Conditions Ratings -0.3 to 7.0 -0.3 to 7.0 VCC supply side pin VCC supply side pin VDD supply side pin VDD supply side pin -0.3 to VCC+0.3 -0.3 to VCC+0.3 -0.3 to VDD+0.3 -0.3 to VDD+0.3 200 -20 to +85 -40 to +125 Unit V V V V V V mW C C
MITSUBISHI (Dig./Ana. INTERFACE)
M62376GP
8-BIT 12CH D-A CONVERTER IC BUILT-IN 12-BIT I/O EXPANDER
ELECTRICAL CHARACTERISTICS RECOMMENDED OPERATING CONDITION
Symbol VCC VDD VIN VOUT VIN VOUT Parameter Digital supply voltage Analog supply (D-A converter upper reference voltage) Input pin voltage (VCC part) Output pin voltage (VCC part) Input pin voltage (VDD part) Output pin voltage (VDD part) Conditions Ratings 2.7 to 5.5 2.7 to 5.5 0 to VCC 0 to VCC 0 to VDD 0 to VDD Unit V V V V V V
VDDVCC EN, SI, D0 to D3 SO, D0 to D3 RESET, D4/A12 to D11/A5 A1 to A4, D4/A12 to D11/A5
DIGITAL PART [VCC] (VCC=2.7 to 5.5V, Ta=-20 to +85C, unless otherwise noted)
Symbol VCC ICC IILK VIL VIH VOL VOH VT+ VTParameter Supply voltage Supply current Input leak current Input low voltage Input high voltage Output low voltage Output high voltage Forward threshold voltage (EN, CLK) Backward threshold voltage (EN, CLK) Test conditions Min. 2.7 - -10 0.5VCC IOL=2.5mA IOH=-400A 0.4 VCC-0.4 0.5VCC 0.2VCC Limits Typ. 3.0 Max. 5.5 2.5 10 0.2VCC Unit V mA A V V V V V V
CLK=1MHz operation, VCC=3V, IAO=0A VIN=0 to VCC
DIGITAL PART [VDD] (VDD=2.7 to 5.5V, Ta=-20 to +85C, unless otherwise noted)
Symbol VDD IILK VIL VIH VOL VOH Parameter Supply voltage Input leak current Input low voltage Input high voltage Output low voltage Output high voltage Test conditions Min. 2.7 -10 0.5VDD IOL=2.5mA IOH=-400A 0.4 VDD-0.4 Limits Typ. 3.0 Max. 5.5 10 0.2VDD Unit V A V V V V
VIN=0 to VDD
Note. For circuit current of VDD, see the analog block.
ANALOG PART (VDD (VrefU) =2.7 to 5.5V, Ta=-20 to +85C, unless otherwise noted)
Symbol IDD VDD (VrefU) Parameter Dissipation current D-A converter upper reference voltage range Test conditions VrefU=3V input data condition: When maximum current of R-2R rudder is supplied
In the setup range of reference voltage, all values are not taken with output. Values to be taken depend on the item of buffer amplifier output voltage range.
Min. -
Limits Typ. 1.5
Max. 3.5
Unit mA
2.7 0.1 0.2 -0.3 -1.0 -1.5 -2.0 -2.0 5
5.5 VDD-0.1 VDD-0.2 1 1.0 1.5 2.0 2.0 10
V
VAO
Buffer amplifier output voltage range
IAO SDL SL SZERO SFULL CO RO
Buffer amplifier output drive range Differential nonlinearity error Nonlinearity error Zero code error Full scale error Output capacitative load Buffer amplifier output impedance
IAO=100A +500A IAO= -200A Upper side saturation voltage=0.4V Lower side saturation voltage=0.4V VDD=2.700V (VrefU) Without load (IAO=+0A)
V
mA LSB LSB LSB LSB F
MITSUBISHI (Dig./Ana. INTERFACE)
M62376GP
8-BIT 12CH D-A CONVERTER IC BUILT-IN 12-BIT I/O EXPANDER
AC ELECTRICAL CHARACTERISTICS (VCC, VDD=2.7 to 5.5V, Ta=-20 to +85C, unless otherwise noted)
Symbol tCKL tCKH tCR tCF tDCH tCHD tCLH tCHL tENH tSO tDO tLDD Parameter Clock low pulse width Clock high pulse width Clock rise time Clock fall time Data setup time Data hold time Clock (EN) setup time EN setup time EN high hold time Serial data output delay time Parallel data output delay time D-A output settling time Test conditions Min. 200 200 Limits Typ. Max. Unit ns ns 200 30 60 100 200 200 CL=100pF CL=100pF CL100pF, VAO:0.1 2.6V Until output takes 2LSB of the final value. 350 600 100 ns ns ns ns ns ns ns ns s
INPUT
DUT CL
OUTPUT
TIMING CHART
tENH EN tCLH CLK tCKL SI D0 to D11 INPUT D0 to D11 OUTPUT tSO SO OUTPUT tLDD A0 to A11 OUTPUT tDO tDCH tCHD tCR tCKH tCF tCHL
tDCH
tCHD
MITSUBISHI (Dig./Ana. INTERFACE)
M62376GP
8-BIT 12CH D-A CONVERTER IC BUILT-IN 12-BIT I/O EXPANDER
APPLICATION EXAMPLE
VDD VCC
13 VDD DAC OUTPUT
ADJUSTMENT PINS FOR ANALOG IC SHARED PINS FOR DAC AND I/O
14 VCC (*) RESET EN SO SI CLK 23 22 21 MCU 20 19
1 2 3 4 5 6 7
A1 A2 A3 A4 D11/A5 D10/A6 D9/A7 D8/A8 D7/A9 D6/A10 D5/A11 D4/A12 GND 24 D0 D1 D2 D3 18 17 16 15
DAC OUTPUT
ADJUSTMENT PINS FOR ANALOG IC
8 9 10 11 12
I/O LOGIC IC
COMPARATOR
I/O LOGIC IC
COMPARATOR
PRECAUTION FOR USE
This IC has two power supply pins and a ground pin. Superimposition of these pins with ripple and spike noise may cause reduction of conversion accuracy and occurrence of malfunction. Be sure to insert a capacitor between each power supply and the GND pin to stabilize D-A converting operation. The output buffer amplifier of this IC has strong characteristics against capacitive load. Accordingly, when the capacitance (10F MAX.) is connected between output and ground to remove jitter and noise due to installation of output line, no problem may occur in operation of DAC. However, notice that the removal results in lengthening the settling time. This IC also provides power-on reset function. To assure the resetting operation, power supply should be turned on in the order of timing shown in the diagram below. (Order): 1. VCC 2. VDD
VDD VCC
(*) The RESET pin is directly connected with the power pin to use power-on reset. However, when forced reset is done from outside, the capacitance (0.1 to 10F) should be connected between RESET pin and ground to remove noise due to installation of line, etc.
Time t
Fig. 1 Order for power-on

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